Continuous-time adaptive learning circuit

ABSTRACT

An integrator-multiplier-integrator circuit scheme usable in transverse  fers, a transverse filter employing such a circuit, and a method for using each. The multiplier-integrator-multiplier has a capacitatively loaded integrating amplifier fed by a transistor. The current through the transistor, and hence the time it takes to charge the integrating capacitor, depends largely on the bias of the transistor, not the size of the capacitor, permitting one to set and control integration time by setting the transistor&#39;s parameters, and controlling its bias, effectively controlling integration time by us of only one semiconductor device. An additional circuit for auto-zeroing (i.e. canceling quiescent offset) increases adaptivity of the circuit. Preferably the phase of inputs to the first multiplier is made selectably variable to minimize phase difference at the multiplier, thus increasing circuit stability.

BACKGROUND OF THE INVENTION

Adaptive filter circuits which employ the least mean square learningalgorithm have widespread applications, which are continually growing innumber. These adaptive filters employ a number of circuit legs whichsequentially multiply a time delayed reference input signal with anerror signal, integrate the product, and multiply the integrated productwith the reference input delayed signal. The longer the time constant ofthe integrator circuit, the more desirable is the integrator because itcan effectively integrate over longer time periods. Long integrator timeconstants are useful for adaptive filter circuits because they increasethe range of applications for which the adaptive filter can be used. Forexample, the smallest notch filter bandwidth that can be achieved by anadaptive filter is often determined by the length of the time constant.Also, minimum filter adaptive filter operation frequency is severalorders of magnitude higher than the corner frequency of the integrator,so that a large time constant extends the allowable frequency ofoperation of the adaptive filter. Conventional integrator circuits, suchas simple RC networks cannot produce sufficiently long time constants,generally equal to RC, for many applications because the physical sizeof the capacitors would necessarily be too large for integratedsemiconductor chips; and it is difficult to fabricate high valueresistors with conventional integrated circuit technology.

Additionally, many integrator circuits when used in integrated circuitshave unacceptably poor high frequency response for many adaptivelearning applications, further limiting the usefulness of thesecircuits. For example, the frequency of operation of switched capacitorintegrators is limited by the need for high amplifier bandwidth toprovide sufficient settling accuracy for sampled-data signal processing.

One approach is reflected in U.S. patent application Ser. No. 07/984,111by Kub and Justh Kub et al. (attorney docket no. 74,832), currentlypending. Kub et al. disclose an integrator-multiplier-integrator inwhich the integrator is a transconductance-C circuit, and which theintegration time is controlled largely by FET parameters. It is,however, desirable in this art to extend the level of adaptivity of suchcircuits that can be achieved by the adaptive filter circuit. The levelof adaptivity that can be achieved by the transconductance-C integratorapproach is limited by random offset voltages and limited gain.

SUMMARY OF THE INVENTION

Accordingly, an object of the invention is permit fabrication ofintegrator circuits having a large time constant without use of highvalue resistors (>1 MΩ).

Another object is to provide continuous-time (i.e. not sampled data)multiplier-integrator-multiplier circuit legs having good high frequencyperformance.

Another object is to do the foregoing in a manner which will permitrealization of such circuit legs in monolithic semiconductor chips,using state of the art semiconductor fabrication techniques.

Another object is to achieve high levels of adaptivity.

Another object is to increase the bandwidth of operation of the adaptivefilter circuit.

Aspects of the invention are touched on by Kub and Justh, High FrequencyAnalog Circuits Implementing Tapped Delay Lines and the LMS Algorithm,which appears in Proceedings of the 1994 Adaptive Antenna SystemsSymposium (Nov. 7-8, 1994, hosted by the Long Island Section of theInstitute of Electrical and Electronics Engineers), which isincorporated herein by reference. More broadly, these and other objectsare secured in accordance with the various features and advantages ofthe invention. In accordance with one feature, amultiplier-integrator-multiplier has a capacitatively loaded integratingamplifier fed by a transistor. The current through the transistor, andhence the time it takes to charge the integrating capacitor, dependslargely on the bias at the gate of the transistor, not the size of thecapacitor. In this manner, one can set and control integrating time bysetting the transistor's parameters, and controlling its bias, thuscontrolling integration time by controlling one semiconductor device. Inaccordance with another feature, a semiconductorintegrator-multiplier-multiplier has an additional circuit forauto-zeroing (canceling quiescent offset), thus increasing adaptivity ofthe circuit. In accordance with another feature, the phase of inputs tothe first multiplier is selectably varied to minimize phase difference,between the multiplier inputs, thus increasing circuit stability,bandwidth, and adaptivity.

These and other objects, features, and advantages of the invention arefurther understood from the following detailed description of particularembodiments of the invention. It is understood, however, that theinvention is capable of extended application beyond the precise detailsof these embodiments. Changes and modifications can be made to theembodiments that do not affect the spirit of the invention, nor exceedits scope, as expressed in the appended claims. The embodiments aredescribed with particular reference to the accompanying drawings,wherein:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit schematic showing a prior art transverse filter,having four multiplier-integrator-multiplier legs.

FIG. 2 is a circuit schematic showing a multiplier-integrator-multipliercircuit useable, e.g., in the filter of FIG. 1.

FIG. 3 is a circuit schematic showing an alternative integrator scheme.

FIG. 4 is a circuit schematic showing an auto-zeroing circuit forintegrators, such as are shown in FIGS. 2-3.

FIG. 5 is a circuit schematic showing similar to that of FIG. 1, withadditional phase-control circuitry.

DETAILED DESCRIPTION

With reference to the drawing figures, wherein like references indicatelike parts throughout the several views, FIG. 1 shows a prior arttransverse filter having four cancellation legs. The circuit receives aninput signal 19, and a sum signal 21 at signal adder 18, and a referencesignal 11, 13 at delay element 10. (Why each signal is denominated bytwo references will become apparent in the discussion of FIGS. 2 ƒƒ.)The input and reference signals could, for example, be a radar echocombined with jammer noise, a jammer noise, respectively, such as onewould get with conventional military radar systems using a mainbeamantenna for the main signal, and a spatially distant auxiliary antennafor the reference signal.

The main signal 19 subtracted from the sum signal 21 via summer 18 andis fed in parallel to a first multiplier 20, 22, 24, 26 in eachrespective leg of the filter. The reference signal is also fed to thesemultipliers, but cumulatively shifted in phase at each leg by delays 10,12, 14, and 16. Each leg outputs the product of the main, and timedelayed reference, signals to respective integrators 28, 30, 32, 34.Each leg contains a second multiplier, 36, 38, 40, 42, respectively,which multiply integrator output with the time delayed reference inputinto the leg's first and second multipliers. (E.g., multiplier 36multiplies the output of integrator 28 with the reference signal delayedby an amount τ₁ by delay 10; multiplier 40 multiplies the output ofintegrator 32 with the reference signal delayed output from delay 14,and hence delayed by τ₁ +τ₂ +τ₃, etc.) Summer 44 receives and adds theoutputs of each second multiplier 36, 38 40, 42, and directs this sum tosubtractor 18, where the sum is subtracted from the main input signal,yielding an error signal 15, 17, which is also a corrected main signal45.

Such circuit are well known as an interference canceler. Generallyspeaking, each pair of cancellation legs (20, 28, 36 being one leg, and22, 30, 38 being another such leg) permits cancellation of one unwantedfrequency or interference in the main signal, provided one has someknowledge of what those frequencies or interferences might be, and hencejudiciously selects the values of τ accordingly. If so, the output ofeach integrator will converge to a weight value which causes optimalcancellation of unwanted frequencies at the output of 18, which is thecorrected main signal 45 (i.e. optimally given the values of τ, whichmay or may not themselves be optimal for the specific frequencies onemay wish to cancel).

FIG. 2 shows a circuit leg, of the type above described in FIG. 1,according to the invention. (For simplicity, part numbers will be thatof the first leg shown in FIG. 1, i.e. 20, 28, and 36.) The error signalarrives via lines 15, 17, which are marked respectively "+" and "-",i.e. to indicate that the signals on lines 15 and 17 are the inverse ofeach other (180° apart). Similarly, the reference signal appears at 11,13 similarly the inverse of one another, and are input to multiplier 20with an additional time delay, or phase shift, τ₁ with respect to themain signal. Providing the main and reference signals as separate "plus"and "minus" lines permits use of four-quadrant multipliers (e.g. Gilbertmultipliers) at 20 and 36, which experience shows provides best resultsfor cancelling harmonics, and is most compatible with C-MOS (n.b. FET)technology. The lines carrying the reference signal to the firstmultiplier 20 may also have an additional phase shift δ per time delayelement 46. The reference is also applied to the second multiplier 36,for reasons discussed below.

The two quadrant current output (i.e. "plus" and "minus" outputs) ofmultiplier 20 is input to current to voltage converter 48. Four quadrantC-MOS multipliers such as the Gilbert multiplier produce an outputsignal in current form. A current signal could, in principle, be inputdirectly into an integrator such as 28, but this would result in a largeintegrated current per magnitude of input signal, much of which wouldcorrespond only to quiescent current flowing in multiplier 20. Thiswould require larger integration capacitors, a shorter integration time,and a less accurate integrated signal. It is thus preferred that theinputs 49, 51 to integrator 28 be voltages, rather than currents. Thiscurrent to voltage converter 48 does the required current to voltagetranslation.

The "plus" and"minus" outputs of converter 48 go respectively to FET's50, 52, and thereafter to the inverting inputs of difference amplifiers56, 58. FET's 50 and 52 are biased (53) to pass the same amount ofcurrent, and hence constitute the same absolute value of current betweensource and drain, for the same absolute value of input voltage signal at49, 51. In this manner, FET's 50, 52 produced a balanced "plus" and"minus" two-quadrant input to amplifiers 56, 58. The biases to thenon-inverting inputs to amplifiers 56, 58 can be set in any mannerconsistent with their operating parameters; however, experience withC-MOS technology indicates that the setpoint, or quiescent operatingpoint, of current to voltage converter 48 is about the same as one wouldneed for C-MOS operational amplifiers, and thus amplifiers 56, 58 arebiased at converter 48's setpoint via line 54.

Amplifiers 56, 58 have corresponding capacitors 60, 62 in theconfiguration of a conventional integrator. Thus the two-quadrantsignals from lines 49, 51 via FET's 50, 52 are integrated, and input tofour quadrant multiplier 36, where the integrated signal is multipliedwith the delayed (by τ₁) reference signal 11, 13 and output to summer44, as described above. Thus the circuitry of FIG. 2 constitutes amultiplier-integrator-multiplier circuit of the kind used in theadaptive filter of FIG. 1. Notably, however, The rate at whichcapacitors 60 and 62 charge depends on the amount of current which FET's50, 52 permit to pass, which in turn depends on their bias 53. Thus thetime constant of the integrators depends largely on the gain parametersof FET's 50, 52, not on bulk-size. Thus the circuit according to FIG. 2can be made smaller for the same integration times, and thus more suchcircuits could be put on one chip.

FIG. 3 shows an alternative to the integrator of FIG. 2. Instead of twodifference amplifiers biased to the same setpoint, amplifier 64 isconventional balanced amplifier with common mode feedback, i.e. theamplifier's outputs are set to a well-defined operating point by thecommon mode feedback circuitry. This dispenses with the need to providea separate setpoint bias to integrator 64, as was done at 54 in FIG. 2.

FIG. 4 shows additional circuitry for autozeroing a circuit such as thatin FIG. 2, i.e. correcting for non-zero outputs resulting from zeroinputs at 11, 13, 15, 17 (e.g. cumulative quiescent offsets from thevarious devices in the circuit of FIG. 2.). Amplifier 58 has associatedwith it an additional amplifier 66, whose output is subtracted from thatof amplifier 58 at summer 68. Switches 78, 80 permit selective isolationof the inputs to amplifier 66, and switch 74 permits selective isolationintegration of capacitor 60. The inputs to amplifier 66 have parallelcapacitors 70, 72. Associated with capacitor 60 is a switch, preferablya FET switch 74, which can open to isolate capacitor 60 from thecircuit. The switches are controllably biased to open or closesimultaneously by bias 76, and preferably FET's to permit integralfabrication of all circuit elements on one chip.

In operation, all circuit inputs of the first multiplier 20 aredisconnected from the error signals 15, 17, and the reference signals11, 13, and connected in common to a bias voltage by transistor switcharrangements (not shown), switches 80, 78 closed, and switch 74 opened.Any residual non-zero output from amplifier 58 is fed back via summer 68(which can include a gain element, not explicitly shown) via line 69 andswitch 78 to amplifier 66, which outputs a signal to summer 68 thatsubtracts from the output of amplifier 58. This reduces the output from68 fed back to amplifier, and, similar to a servo-controller, the outputof 66 eventually stabilizes at the magnitude necessary to balance theoutput of 58. The corresponding input signal (via switch 78) toamplifier 66 which causes this balance charges capacitor 70, thusrecording this input on capacitor 70. (Switch 80 and capacitor 72operate in the same manner to record the bias voltage on amplifier 66presence when this balance occurred.) Switches 78, 80 are then opened toprevent further charging or discharging of capacitors 70, 72, and switch74 is closed to permit normal operation of the circuit responsive toinput signals. In the foregoing, only integrator 58, 60 is mentioned. Itis understood, however, that in a circuit such as in FIG. 2 which hastwo such integrators to produce a two-quadrant output will need anauto-zeroing circuit of this kind for each integrator.

FIG. 5 shows a general transverse filter like that of FIG. 1, with theaddition to each leg a corresponding delay 46₁, 46₂, 46₃, and 46₄, andcomplex amplifier 82. If the two inputs to the first multiplier (20, 22,24, 26 for the four legs, respectively) of any of the circuit legs aresignificantly different in time delay (phase shift), filter performancecan degrade sharply. (Experience shows that if the phase exceeds 45°,the filter can oscillate.) Each delay 46 is preferably programmable, andset to phase match the inputs to multipliers 20, 22, 24, 26, in anyknown manner, e.g. by multiple delay stages with integral switch-in andswitch-out circuitry.

Amplifier 82 provides a complex gain which boosts the amplitude of thesignal output from summer 44 to match the amplitude of the main signalinput to member 18, and adds undesired phase shift to the sum signal 21.Phase shift element 46 is designed to compensate for the phase shift ofamplifier 82, and any other phase shift in the feedback path. Inpractice, virtually all of this phase shift occurs between the output ofsummer 44 and the input of summer 18, so placement of amplifier 82 inthis line is not only effective, but preferred.

The invention has been described in what is considered to be the mostpractical and preferred embodiments. It is recognized, however, thatobvious modifications to these embodiments may occur to those with skillin this art. Accordingly, the scope of the invention is to be discernedfrom reference to the appended claims, wherein:

We claim:
 1. A multiplier-integrator-multiplier circuit comprising:afirst multiplier; an integrator adapted to receive the output of saidmultiplier; and a second multiplier adapted to receives the output ofsaid integrator; wherein said integrator comprises:a differenceamplifier; an integrating capacitor in parallel with said differenceamplifier; and a transistor, the output of said transistor disposed toconstitute the input of said difference amplifier; wherein said circuitfurther comprises an auto-zero circuit, said auto-zero circuitcomprising:means for isolating said capacitor and isolating the input tosaid difference amplifier; and a further capacitor disposed in parallelwith the output of said input of said difference amplifier, and saidoutput of said integrator.
 2. A multiplier-integrator-multiplier circuitcomprising:a first multiplier; an integrator adapted to receive theoutput of said multiplier; and a second multiplier adapted to receivethe output of said integrator; wherein said integrator comprises:adifference amplifier; an integrating capacitor in parallel with saiddifference amplifier; and a transistor, the output of said transistordisposed to constitute the input of said difference amplifier;wherein:said difference amplifier is a pair of difference amplifiersdisposed to cause said integrator to be a two-quadrant integrator; andsaid transistor is a pair of transistors, one each of said pair oftransistors disposed so that the output of said one each of said pair oftransistors is the input of a respective one of said pair of differenceamplifiers; wherein said circuit further comprises an additionaldifference amplifier for auto-zeroing the output of at least one of saidpair of difference amplifiers, wherein:one input of said additionaldifference amplifier is disposed to receive: a preselectable calibrationsignal, and said output of said circuit; the other input of saidadditional difference amplifier is disposed to receive the output ofsaid circuit; wherein said circuit further comprises a summing junctiondisposed to receive the output of said at least one of said differenceamplifiers and the output of said additional difference amplifier. 3.The circuit of claim 2, wherein each said input of said additionaldifference amplifier has an associated capacitor, each said capacitorbeing disposed effective to hold a charge, responsive to said one andsaid other input of said additional difference amplifier, correspondingto auto-zero setpoint for said circuit.
 4. Amultiplier-integrator-multiplier circuit comprising:a first multiplier;an integrator adapted to receive the output of said multiplier; and asecond multiplier adapted to receive the output of said integrator;wherein said integrator comprises:a difference amplifier; an integratingcapacitor in parallel with said difference amplifier; and a transistor,the output of said transistor disposed to constitute the input of saiddifference amplifier; wherein said difference amplifier is a pair ofdifference amplifiers disposed to cause said integrator to be atwo-quadrant integrator; and said transistor is a pair of transistors,one each of said pair of transistors disposed so that the output of saidone each of said pair of transistors is the input of a respective one ofsaid pair of difference amplifiers; wherein said pair of differenceamplifiers is a unitary balanced amplifier with common mode feedback,and said transistor is a pair of transistors, one each of said pair oftransistors disposed so that the output of said one each of said pair oftransistors is the input of a respective input of said balancedamplifier.
 5. A multiplier-integrator-multiplier circuit comprising:afirst multiplier; an integrator adapted to receive the output of saidmultiplier; and a second multiplier adapted to receive the output ofsaid integrator; wherein said integrator comprises:a differenceamplifier; an integrating capacitor in parallel with said differenceamplifier; and a transistor, the output of said transistor disposed toconstitute the input of said difference amplifier; wherein said circuitfurther comprises an additional difference amplifier for auto-zeroingthe output of said circuit, wherein:one input of said additionaldifference amplifier is disposed to receive: a preselectable inputsignal, and said output of said circuit; the other input of saidadditional difference amplifier is disposed to receive: the output ofsaid circuit; wherein said circuit further comprises a summing junctiondisposed to receive the output of said integrator and said additionaldifference amplifier.
 6. The circuit of claim 5, wherein each said inputof said additional difference amplifier has an associated capacitor,each said associated capacitor being disposed effective to hold acharge, responsive to the inputs to each corresponding said input tosaid additional difference amplifier, corresponding to auto-zerosetpoint for said circuit.
 7. A multiplier-integrator-multiplier circuitcomprising:a first multiplier; an integrator adapted to receive theoutput of said multiplier; and a second multiplier adapted to receivethe output of said integrator; wherein said integrator comprises:adifference amplifier; an integrating capacitor in parallel with saiddifference amplifier; and a transistor, the output of said transistordisposed to constitute the input of said difference amplifier; andwherein the input of said first multiplier comprises a phase shiftereffective to cause a preselected phase at said input.
 8. A transversefilter comprising:a plurality of multiplier-integrator-multipliercircuit legs effective to produce a corresponding plurality of outputsignals; means for inputing a main signal to said filter; means forinputing an error signal to said filter; means for summing saidcorresponding plurality of outputs to form a feedback signal; subtractormeans for differencing said feedback signal and said main signal; anadjustable phase shifter effective to selectable reduce the phasedifference between said feedback signal and said main signal; wherein atleast one of said circuit legs comprises:a first multiplier; anintegrator adapted to receive the output of said multiplier; and asecond multiplier adapted to receive the output of said integrator;wherein said integrator comprises:a difference amplifier; an integratingcapacitor in parallel with said difference amplifier; and a transistor,the output of said transistor disposed to constitute the input of saiddifference amplifier.
 9. The circuit of claim 8, wherein the input tosaid transistor comprises a current to voltage converter.
 10. Thecircuit of claim 9, wherein the input of said first multiplier comprisesa phase shifter effective to cause a preselected phase at said input.11. A method of filtering a signal using a transverse filter, saidfilter comprising a multiplier-integrator-multiplier circuit, saidcircuit comprising a first multiplier, an integrator, a secondmultiplier, and a transistor, said integrator comprising a differenceamplifier and an integrating capacitor in parallel with said differenceamplifier, the output of said transistor being disposed to constitutethe input of said difference amplifier, wherein said methodcomprises:causing said first multiplier to receive an input; causingsaid integrator to receive the output of said first multiplier; causingsaid second multiplier to receive the output of said integrator; settingthe bias of said transistor effective to selectably set the timeconstant of said integrator; wherein said difference amplifier is a pairof difference amplifiers disposed to cause said integrator to be atwo-quadrant integrator; and said transistor is a pair of transistors;wherein said method further comprises disposing said pair of transistorsso that the output of each of said pair of transistors is the input ofthe respective other of said pair of difference amplifiers; wherein saidcircuit further comprises an additional difference amplifier forauto-zeroing the output of at least one of said pair of differenceamplifiers, and wherein:one input of said additional differenceamplifier is disposed to receive: a preselectable calibration signal,and said output of said circuit; and the other input of said additionaldifference amplifier is disposed to receive the output of said circuit;wherein said method comprises summing the output of said at least one ofsaid difference amplifiers and the output of said additional differenceamplifier.
 12. The method of claim 11, wherein each said input of saidadditional difference amplifier has an associated capacitor, each saidcapacitor being disposed effective to hold a charge, corresponding toauto-zero setpoint for said circuit, said method further comprisingselectably charging each said capacitor to fix said setpoint.
 13. Amethod of filtering a signal using a transverse filter, said filtercomprising a multiplier-integrator-multiplier circuit, said circuitcomprising a first multiplier, an integrator, a second multiplier, and atransistor, said integrator comprising a difference amplifier and anintegrating capacitor in parallel with said difference amplifier, theoutput of said transistor being disposed to constitute the input of saiddifference amplifier, wherein said method comprises:causing said firstmultiplier to receive an input; causing said integrator to receive theoutput of said first multiplier; causing said second multiplier toreceive the output of said integrator; setting the bias of saidtransistor effective to selectable set the time constant of saidintegrator; wherein said difference amplifier is a pair of differenceamplifiers disposed to cause said integrator to be a two-quadrantintegrator; and said transistor is a pair of transistors; wherein saidmethod further comprises disposing said pair of transistors so that theoutput of each of said pair of transistors is the input of therespective other of said pair of difference amplifiers; wherein saidpair of difference amplifiers is a unitary balanced amplifier withcommon mode feedback, and said transistor is a pair of transistors, andsaid method further comprises causing one each of said pair oftransistors to be disposed so that the output of said one each of saidpair of transistors is the input of a respective input of said balancedamplifier.
 14. A method of filtering a signal using a transverse filter,said filter comprising a multiplier-integrator-multiplier circuit, saidcircuit comprising a first multiplier, an integrator, a secondmultiplier, and a transistor, said integrator comprising a differenceamplifier and an integrating capacitor in parallel with said differenceamplifier, the output of said transistor being disposed to constitutethe input of said difference amplifier, wherein said methodcomprises:causing said first multiplier to receive an input; causingsaid integrator to receive the output of said first multiplier; causingsaid second multiplier to receive the output of said integrator; settingthe bias of said transistor effective to selectably set the timeconstant of said integrator; wherein said circuit further comprises anadditional difference amplifier for auto-zeroing the output of saidcircuit, wherein:one input of said additional difference amplifier isdisposed to receive a preselectable input signal, and said output ofsaid circuit; the other input of said additional difference amplifier isdisposed to receive: the output of said circuit; wherein said methodcomprises summing the output of said integrator and said additionaldifference amplifier.
 15. The method of claim 14, wherein each saidinput of said additional difference amplifier has an associatedcapacitor, each said associated capacitor being disposed effective tohold a charge, responsive to the inputs to each corresponding said inputto said additional difference amplifier, corresponding to auto-zerosetpoint for said circuit, and said method further comprises chargingsaid capacitors to selectably determine said setpoint.